Research On Hybrid Architecture Analog-to-Digital Converter Based On Flash And Successive-Approximation Resister Structure

Analog-to-digital converter(ADC)which is one of the most important chips in the information age.ADCs can convert analog signals widely existed in nature into digital signals which can be utilized by electronic systems,becoming a bond or bridge between the real world and digital domian.With the pursuit of efficient high-speed communi-cation,ADCs as communication system interfaces should also have smaller size,lower power consumption and higher performance.However,due to the limitations of semi-conductor process,Traditional ADC architectures have been difficult to meet the needs of existing applications,so some hybrid architectures have been proposed.Nowadays,many kinds of hybrid architectures shine,which has advantages over traditional archi-tectures.This thesis proposes an ADC based on successive approximation register(SAR)and Flash architectures,which can double the conversion rate by using two capacitive digital-to-analog converter(DAC)arrays and three comparators while at a small cost of power and area.The two capacitor arrays are SIG-DAC,which is used to sampling the input signal and generating the residual voltage,and the REF-DAC,which is respon-sible f'or generating the reference voltage.To ensure that the system is robust enough to comparator offset variations and mismatch between DACs,the capacitor DACs are designed to be nonbinary weighted,which can give the system a redundant design.Moreover,both the SIG-DAC and REF-DAC use the monotonic switching technology in the proposed hybrid architecture,which can significantly reduce the power consump-tion,making the ADC have certain advantages in FoM.Meanwhile,in order to improve the conversion speed,this ADC uses asynchronous control logic to optimize the shift register and data registers and the digital logic on the critical path,which improves the time utilization and also reduces the power consumption a little bit.The hybrid architecture ADC designed in this thesis was tapeout in the GF 130nm SOI process,with a core area of 245μm × 300μm.At 1.2V power supply and 100MHz sampling rate,the simulation results shows a signal-to-noise distortion ratio(SNDR)of 50.82dB and a spurious-free dynamic range(SFDR)of 53.32dB.The total power consumption of the ADC is 0.732mW and the FoM is 25.7 fJ/conversion-step.