Design Of Full Differential Successive Approximation ADC With A Monotonic Capacitor Switching Procedure

Successive approximation ADC,it's also known as SAR ADC,successive approximation comes from the operating mode of the approximation level.Compared with other architecture ADCs,it has a simple structure,low power consumption,low cost and low accuracy area,SAR ADC has a simple structure,its functions is similarly to a digital circuit,it's mainly active in many fields such as wireless sensor networks,data / signal collectors,digital video and it is widely used in currently.The traditional high-precision ADC implementation architecture is the pipelined ADC or the oversampling ADC.The successive approximation of analog-to-digital converters has high digitalization,simple architecture,small area and low power consumption.It can achieve a very low quality factor.In addition,the pipeline delay and the delay of the oversampling decimation filter are not suitable for the field of high-speed response,etc.but the SAR ADC can well meet the requirements of high-speed response.The successive approximation analog-to-digital converter is more used in the low power consumption and low speed field.In recent years,semiconductor design and manufacturing have developed rapidly,it's endless to research on CMOS devices,they are all committed to researching smaller CMOS feature sizes.As the feature size continues to shrink,the difficulty of research becomes greater and greater,the size is getting closer to the limit of Moore's Law,the speed of the device is demanding faster and faster,with the improvement of technology and crafts,Constantly refresh the SAR ADC's indicators to the higher end.This article shows the research and design of a 10-bit 1MS / s successive approximation analog-to-digital converter.A shift register is used for synchronous clock control.In order to reduce power consumption,each time the switch of the DAC capacitor array on one side is used,a monotonic capacitor switching algorithm is used in this review.In order to increase the speed of comparison,the comparator with high gain is applied.In the 0.18 um 1P6M CMOS process,analog power supply is 3.3V,digital power supply is 1.8V,an input frequency of 487.3046875 kHz is used for dynamic performance.The layout area is 0.46mm2,the post-imitation Enob is 9.72 bits,the signal-to-noise ratio SNDR is 60.23 dB,the spuriousfree dynamic range SFDR is 72.8.