The Study Of High Level Model Of High Performance Adpll And Circuit Technique

Phase-locked loop(PLL)is a negative feedback control closed-loop system which can efficiently track the phase of a certain frequency signal.In recent years,with the rapid development of digital circuits,ADPLL circuits have been rapidly developed and widely used as an important part of digital circuits.Compared with traditional analog PLL,digital PLL has faster locking time,better stability,better anti-jamming ability and easy to transplant.Therefore,this paper mainly studies the related technology of all-digital phase-locked loop,establishes the high-level system simulation model and realizes the circuit.The work is organized as follows:(1)The working principle and the mathematical model of phase locked loop are analyzed.The Matlab simulation tool is used to model and verify of the charge pump phase-locked loop,and the influence of related parameters on the performance of phase-locked loop is studied.(2)The working principle and circuit technology of all-digital phase-locked loop are analyzed.The all-digital phase-locked loop with proportional integration structure is modeled,and mathematic module is modeled and simulated.The proportion integral operation is realized with digital loop.Then,the whole structure of digital phase-locked loop is simulated and verified,and the influence of parameters on the performance of phase-locked loop is studied.The high locking speed and high dynamic response of digital phase-locked loop are verified.(3)Based on the high-level model,an all-digital phase-locked loop is realized by using proportional integration strategy.When the input frequency is changed,the proportional integral parameters in the top layer of the loop module can be adjusted to enable it to be locked.The range of frequency tracking is widened.Based on Quartus II software,the digital phase detector,digital filter,numerical control oscillator and whole PLL are designed.The whole circuit is compiled and synthesized,and the function simulation and analysis of each module and the whole circuit are completed.Hardware testing is also performed on FPGA platform.Due to the limitation of the input frequency of CMOS data interface,the performance parameters of the DPLL are tested at the input frequency of 100 MHz and 200 MHz in this paper.FPGA verification results show that when the input frequency is 200 MHz,the locking time is 8.4?s,phase noise is-109 d Bc / Hz at 1 MHz frequency offset and-85 d Bc / Hz at 1 k Hz frequency offset respectively.When input frequency is 100 MHz,the locking time is 10.1?s,the phase noise is-113 d Bc / Hz at 1 MHz frequency offset and-98 d Bc / Hz at 1 k Hz frequency offset.The ADPLL circuit has the advantages of good stability,fast locking speed,easy integration,flexible control and good tracking performance.