The Implementation Of Arbiter PUF On FPGA

Physical unclonable function(PUF)is a promising hardware security technology,which can ensure the storage security of encryption and decryption keys used in traditional encryption algorithms such as AES and RSA during.As one of the many physical unclonable functions,Arbiter PUF has attracted wide attention due to its simple structure,rich "ChallengeResponse" pairs and low cost.The Arbiter PUF uses the difference of the transmission delay of the symmetric path to generate a response.Therefore,the requirements for the symmetric path are very strict.The implementation of the arbiter PUF on the FPGA is often subject to the internal wiring of the FPGA,so it performs worse than implementation on ASIC which signal path is completely symmetrical.This problem will lead to the final response is biased.The paper proposes an adaptive adjustable compensation circuit structure,which aims at the problem of the Arbiter PUF wiring on FPGA is not completely symmetrical.The main structure of the circuit contains the programmable delay line and multiplexer.By looking up the resulting response in a group,find the value that guarantees the best randomness.In addition,the idea of multi-mode redundancy is introduced to improve the stability of the Arbiter PUF.For the same challenge,the most frequently occurring value is selected as the final response after measuring an odd number of times,which is used to reduce the error between each generated response.In order to verify the correctness of the design,the system is built to test the performance of the implemented Arbiter PUF.The software in PC is used to transmit the initial challenge and the final response and calculate the inter Hamming distance and intra Hamming distance.Finally,experiments show that the intra hamming distance is controlled within 4.36%,the inter hamming distance reaches 49.95%,the randomness of responses reach 49.98%,after the Compensation circuit and Multi-mode redundancy are added and realized,and achieve the design goal.