Convolutional Neural Network Accelerator And Its Verilog HDL Code Automatic Generation Design

With the development of convolutional neural network(CNN)and artificial intelligence embedded platforms,deploying CNN application to resource-constrained embedded platform with low-power real-time forward inference has become the focus of current research.While improving the accuracy of CNN model,the depth and number of parameters is also increasing.Traditional processors have been unable to support such a huge amount of computation;therefore,it is necessary to design a corresponding neural network hardware acceleration according to the characteristics of CNN structure to achieve low-power real-time forward inference.In order to facilitate development and deployment,it is also necessary to provide friendly development environment of hardware acceleration system,which can quickly and seamlessly deploy CNN applications to the embedded platform.To tackle the above two problems,this paper proposed a CNN hardware accelerator and its Verilog HDL code automatic generation design.The main work is as follows:1)FPGA-based hardware acceleration design of CNN.The parallel acceleration feasibility of the convolutional layer,the pooling layer,the activation layer and the fully connected layer is analyzed,and then these layer parallel acceleration schemes is designed separately.In the hardware accelerated design of convolutional layer,two computation methods and four parallel parts are proposed according to the feasibility of parallel acceleration.Then proposed two basic units,which are full parallel multi-adder tree and efficient window buffer.Three different parallel acceleration schemes are designed to accommodate different convolutional layer structures.Finally,experiments show that with the comparison of MNIST dataset,the energy efficient ratio of the accelerator proposed in this paper reaches 32.73GOPS/W,which is 34% faster than the existing solutions.2)CNN hardware accelerator Verilog HDL code automatic generation system design.Firstly,the problem of the traditional design method of the CNN accelerator and the automatic code generation are analyzed.To tackle these problems,based on template-based code automatic generation technology,a system is designed to automatically generates CNN hardware Verilog HDL code according to the given json file that contain model structure and data.Then,the system is divided into three main modules according to its function,namely the model analysis module,the data quantization module and the code generation module.After that,the design of the three modules is introduced in detail.Finally,the above system is completed and its function is verified through experiments.And it shows that the system designed in this paper has good flexibility,versatility and scalability.