Research And Implementation Of A New Digital Phase-locked Technology

Due to Phase Locked Loop(PLL)'s good performance,it has been widely used in many fields,such as aerospace,electronic communication,automatic production,atomic physics and so on.With the continuous development of electronic technology and current manufacturing technology,PLL is developing in the direction of low cost,high integration,low power consumption,high working frequency and full digitization,so as to meet the higher needs of production and life.All Digital-phase Locked Loop(ADPLL)overcomes many problems caused by analog circuits in traditional PLL,and it is easier to integrate and transplant.This series of advantages make many specialists and related companies at home and abroad devote themselves to its research.However,ADPLL also has some defects.The quantization error will inevitably be introduced in the analog-to-digital conversion of the input signal,which makes the ADPLL have certain limitations in precision and can not break through the limitation of signal quantization.Many researchers have also studied various ways to solve or avoid this problem.In particular,for reference signals and feedback signals whose frequencies are approximately equal or close to integral multiple,the low phase discrimination resolution leads to the deterioration of the performance of the PLL,Neither the traditional analog phase-locked loop nor the later improved Digital-phase Locked Loop can solve the phase locking of this kind of special signals.In order to solve the problem of complex and difficult integration in the design of PLL,it is difficult to suppress the quantization error of digital phase-locked loop in order to solve the problem of two signals with approximately equal frequency or close to integer multiple in the design of PLL.Firstly,we analyse the process of Analog-to-Digital conversion and find that the Analog-to-Digital Converter(ADC)will form a fuzzy region on each quantization step because of the limitation of its resolution,the stability of the edge measurement resolution in the fuzzy region is very high,and the quantization error is the smallest,which is called edge effect.Based on the characteristics of digital edge effect,a scheme to suppress the quantization error of analog-to-digital conversion is designed.the edge algorithm is used to extract the edge data of analog-to-digital converter in dynamic acquisition for detection of the digital phase.Secondly,on Quartus II 13.1 platform,we make use of Verilog HDL hardware development language and top-down design method,the digital phase detector and numerical control oscillator of ADPLL are designed and the integrated logic layout is completed.In the design process,Matlab tool is used to assist the design of digital phase detector in a Programmable Gate Array(FPGA)and determine the Finite Impulse Response(FIR)filter coefficient.After the comprehensive design is completed,the simulation experiment is carried out by using ModelSim 10.1 software.Finally,the designed FPGA circuit is transformed into hardware,and the hardware circuit of the loop is tested and analyzed by frequency stability and phase noise measuring instrument.The experimental results show that the design scheme is feasible for two signals with approximately equal frequency or close to integral multiple,the locking accuracy of the loop is improved,the phase noise is low,and the output frequency stability is high.The new ADPLL circuit has the characteristics of easy integration,strong portability,flexible use and so on.