Research On Low-Noise Fractional-N PLL With Sub-100 Fs Rms Jitter

The development of modern wireless communication technology has led to increasingly stringent requirements on clock sources in wireless communication systems.As a crucial component in wireless communication systems,the phase-locked loop(PLL)frequency synthesizer serves as the primary means to generate on-chip clocks,with its phase noise performance and frequency accuracy determining the upper limits of the system’s performance.Notably,the realization of a fractional-N PLL frequency synthesizers with sub-100 fs or even lower integrated rms jitter is a prerequisite for various applications in modern wireless communication.This dissertation conducts an in-depth and extensive exploration of the fundamental principles and circuit design of PLL frequency synthesizers.A series of original architectures and related circuit design methodologies for PLL frequency synthesizers is proposed in this dissertation.The research presented herein has successfully developed PLL frequency synthesizer chips with the cutting-edge performance around the world.The innovation and value of this dissertation are primarily manifested as below:1.Research on low-Noise PLL architecture with strong lock-in capability.Existing low-noise phase-locked loop(PLL)architectures,such as subsampling PLLs,carry the risk of losing lock during the locking process.On the other hand,charge pump PLL architectures with strong locking characteristics suffer from poor noise performance.In response to these challenges,this dissertation focuses on the dynamic frequency pull-in process of the PLL and establishes a theoretical analysis model for the nonlinear pull-in dynamics of a Type-II 3rd-order PLL under large frequency differences.The model proposed in this dissertation reveals the necessary conditions for the PLL to have frequency capture capability under significant frequency differences.This research provides a theoretical foundation and design guidance for proposing PLL architectures that simultaneously possess low noise and strong locking characteristics.2.Design and implementation of a low-noise integer-N PLL with time-amplifying phase-frequency detector(TAPFD).Building upon the theoretical analysis model mentioned above,this dissertation proposes a charge pump PLL architecture based on a TAPFD.The proposed architecture,operating under large frequency differences,exhibits stable frequency capture capability.Simultaneously,it leverages the phase domain high gain of the proposed TAPFD to significantly reduce the noise contribution of the charge pump.Furthermore,to achieve the aforementioned noise suppression effectively,this dissertation introduces a circuit design and implementation technology for a low-noise TAPFD to break the power-noise tradeoff of the charge pump.While keeping the power consumption of the charge pump unchanged,the noise contribution is reduced by 24 d B.With the aforementioned techniques,this dissertation successfully develops an integer-N PLL chip with an integrated rms jitter of 60 fs.This chip represents the world’s first millimeter-wave charge pump PLL breaking through the-250 d B figure of merit(Fo M).3.Design and implementation of a low-noise fractional-N PLL based on a dual DTC-assisted TAPFD.On the basis of the above research of an integer-N PLL and addressing the challenges of quantization noise cancellation fractional spur mitigation in fractional-N PLL,this dissertation further introduces a circuit implementation technology for achieving high-resolution DTC.By leveraging the phase-domain gain of the TAPFD,the DTC resolution is improved from the perspective of system architecture,and an input-referred resolution of 150 fs is achieved by employing a DTC with resolution of only 3 ps,avoiding the challenges of directly design a fine-resolution DTC.Furthermore,to tackle with the narrow input linear range of the TAPFD,this dissertation proposes a charge pump PLL architecture based on a dual DTC-assisted TAPFD architecture to reduce the fractional spur from-3 d Bc to-59 d Bc.In this dissertation,a fractional-N PLL with an integrated rms jitter of 37.1 fs in integer-N channel and 45.6 fs in fractional-N channel respectively is presented,which marks the world’s first millimeter-wave fractional-N PLL breaking the 50 fs integrated rms jitter barrier.