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Research On Fast Transient Response Of Amperometric LDO

Posted on:2020-07-17Degree:MasterType:Thesis
Country:ChinaCandidate:W H WuFull Text:PDF
GTID:2428330590483126Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
As application systems such as automotive electronics and microprocessors becoming more complex,there are more applications requiring ampere-level high current.LDO has gradually occupied the application field of 1~5A controlled by switching power supplys in the past due to its simple structure,low cost,high PSRR and fast transient response capability.However,today's power and thermal management trends are to minimize the supply voltage to reduce static power consumption,which causes the load circuit being sensitive to supply voltage fluctuations.Therefore,a major challenge in the design of ampere-level high-current LDOs is to control the fluctuations of the output voltage within a certain tolerance range during high slew rate load current conversion.Based on the above requirements,this paper mainly strengthens the transient response capability of ampere-level high-current LDO systems through four ways:The first way is designing a dual feedback loop LDO,which uses the global voltage mode feedback loop to achieve high steady-state accuracy,and uses the secondary current mode feedback loop to improve the loop response speed of the load current from low to high transition,thereby reducing the output voltage drop and response time.The second way is designing a load current bleeder branch to turn on a additional capacitor discharge path to clamp the output voltage spike and reduce the output voltage settling time when the load current transitions from high to low.The third way is designing a dynamic bias circuit to change the gate drive current of the power transistor by detecting the change of the output voltage when the load current is abrupt,further enhancing the slew rate and improving the current utilization efficiency.The last way is using NMOS power transistor and put it in linear region at full load to reduce the chip area and gate parasitic capacitance.At last,based on HHGrace 0.18?m BiCMOS process,the overall circuit is designed and simulated.The results show that the dropout voltage when driving the current of 1.5A is 100mV;when a full range load current step,The rush voltage is about 8mV,the undershoot voltage is 30 mV,the settling time is less than 10?S,and the FOM value is only 0.049 nS.
Keywords/Search Tags:Dynamic bias, VFL, CFL, Stability
PDF Full Text Request
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