Implementation Of HEVC Binary Arithmetic Encoder And Improvement Of CABAC Algorithm

Multimedia technology has spawned the development of high-definition video,and the video resolution demand has gradually increased to 1080 p high-definition television(HDTV),3840x2160 p ultra-high-definition television(UHDTV)and higher.Because of the huge amount of video data,video coding technology is gradually developing.The H.265/HEVC standard has become the most versatile and efficient video coding standard since 2013,which brings ultra-high compression efficiency and greatly increases the complexity of coding operations.Consequently,optimizing the coding calculation of H.265/HEVC is the focus of current research both at home and abroad.As the entropy coding algorithm of HEVC,CABAC is the bottleneck of the whole coding process.Based on the H.265/HEVC video coding standard,this paper proposes an improvement scheme of CABAC entropy coding algorithm,and uses FPGA to implement the CABAC binary arithmetic coder in an efficient way.The main work of this paper consists of the following two points:(1)In the algorithm improvement part,this paper proposes an acceleration acceleration algorithm based on HEVC for CABAC probability estimation.By packing the encoded data,only one probability estimation update is performed after each group of symbol encoding is completed,which affects the coding efficiency only on a smaller scale,while the encoding speed can be increased to some extent.The experiment results show that,for the encoding of HEVC video images,the improved algorithm only reduces the coding efficiency by 2.15%~3.05% and the coding efficiency increases by an average of 11.3%~19.5% of the coding speed,in exchange for a larger software coding speed.The algorithm has good improvement significance and application value in the field of software HEVC coding.(2)In the hardware implementation part,this paper implements an efficient hardware pipeline structure of binary arithmetic encoder in CABAC coding.The hardware architecture of the encoder is designed and optimized according to the characteristics of the algorithm.The probability state data is stored in SRAM,and the probability estimation updating operation is optimized by using lookup table.The coding data is packaged to simplify the calculation amount brought by the update of the probability estimation,and the SRAM resource usage is well reduced.Binary arithmetic coding uses a multi-stage pipeline structure to support5 4-way parallel encoding,and reduces data dependencies in the calculation process.The simulation results show that the hardware CABAC binary arithmetic coder can complete the encoding of 4 bins per clock cycle,and the average delay is 3~5 clock cycles,also the throughput rate reaches 800Mbin/s,which meets the higher frame rate of 1080 p video real-time hardware encoding requirements.