Design Of Parametric DICE SRAM Model Generator

In the development of aerospace and semiconductor industries,SRAM has been applied to the extremely harsh environment,and DICE can improve the impact of SRAM on radiation.However,the manual design of various models of the DICE SRAM has problems such as large workload and long design cycle,and some human error will have a great impact on the chip,and even rework.In order to effectively solve these problems,models of DICE SRAM can be completed by a parametric design method.This method only requires the designer to provide the basic unit,saving a lot of time and manpower.Therefore,the parametric generation of various models of DICE architecture SRAM is very meaningful.By analyzing the structure and principle of SRAM layout,based on the inheritance and derivation of powerful classes in Python API,this paper proposes the use of pycell layout development tool to complete the parametric design of DICE structure SRAM layout,and defines the parameter range: word line depth(16b-4k),bit line width(2-32),multiplexer width(4,8,16).Then according to the hierarchical structure of the SRAM layout,the standard cell library of the layout is summarized and built to facilitate the instantiation of the upper module.On this basis,based on the hierarchical rules of modules,the parametric design flow of the layout module is proposed,and the parametric design of the layout sub-module and macro module is completed.Finally,the parameterized design of the single-port SRAM layout of the DICE structure was completed under the SMIC 0.18μm process by splicing the layout macro module.In this paper,by analyzing the structure and content of DICE structure SRAM model(including cdl netlist,Verilog model,Lef model and Lib model),based on the structure of each model,the hierarchical rules and basic units of each model are summarized and created.The basic unit library of each model facilitates the instantiation of the upper module.Then,according to the characteristics of each model,the parametric design method of the model and the fast extraction method of time series information based on the linear fitting algorithm are proposed.Finally,the Python text processing method is used to complete the parametric design of cdl netlist,Verilog model and Lef model,and the linear fitting curve of time series information is established.In this paper,the model and timing information fitting curve of DICE structure SRAM are verified respectively: physical rule verification and post-simulation are completed for gds layout and cdl netlist,the results show that the layout and netlist function are correct;for Verilog model,the stimulus file is written.The waveform simulation is completed.The results show that the Verilog model is correct.For the fitting curve of the time series information,the time series information extracted by the simulation tool and the time series information calculated by the fitting curve are compared,and the error is below 5%.The DICE structure SRAM layout and model designed in this paper is similar to the model generated by Artisan's memory compiler.It can be applied to the design process of integrated circuits,which can save a lot of manpower and time,and provides a parametric design for other circuit models in the future method.