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Research And Application Of High Performance Image Processing Architecture Based On Xilinx Zynq MPSoC

Posted on:2020-12-09Degree:MasterType:Thesis
Country:ChinaCandidate:Y ZhangFull Text:PDF
GTID:2428330590993829Subject:Engineering
Abstract/Summary:PDF Full Text Request
Along with the development of image processing technology,a large number of application algorithms have emerged in the field of computer vision.Generally,these algorithms have the characteristics of complex processing flow,large amount of computeing data and strict real-time requirement.Therefore,It is hard for the image processing system with the traditional processor architecture to meet its processing requirements.Combining with the advantages of Field Programmable Gate Array(FPGA)in high-speed parallel computing and processors in processing complex algorithms,it has become an important research direction to co-design software and hardware to improve image processing efficiency.In order to solve the problem that the traditional embedded image processing system has,such as fixed structure,fixed function,and lack of versatility,based on Xilinx's Zynq 7020 embedded platform,an image processing architecture that can be flexibly correspond to different hardware and software partitioning strategies is proposed in this thesis.The architecture is consisted of hardware accelerate processing nodes,configurable hardware processing module,video DMA(VDMA)modules for highspeed communication of hardware and software and processor module.The architecture features are as follows:(1)Divide the processing algorithm into Progarmmable Logic processing parts and Processing System processing parts according to the principle of highest operating efficiency.The VDMA module is used for data interaction between PL and PS to implement cooperation of software and hardware image processing.(2)The hardware acceleration node is implemented by the PL part of Zynq 7020 platform,designed to handle traditional processing algorithms that are difficult to implement or computationally inefficient.The configurable hardware processing module has two different structures,which are suitable for sequential processing and data interactivity processing,respectively.The module can be configured to change its acceleration function multiple times to serve different applications.(3)The Linux operating system and the OpenCV function library are transplanted for the processor,and the image data is sampled during the detection to reduce the detection time.In order to verify the performance and scalability of this architecture,based on this architecture,this paper designs an image processing system that can support applications such as face detection,pedestrian detection and moving target edge detection.The hardware acceleration nodes such as RGB to gray scale,Sobel edge detection,gamma correction,binarization processing and configurable bus modules are implemented to accelerate the above applications.After testing,When the video source has a resolution of 640x480 and a frame rate of 30,compared with using the processor in the Zynq platform to perform pure software processing,under the image processing system,face detection,pedestrian detection,moving target edge detection and other applications get 11.95,4.68,8.08 times the acceleration effect respectively.
Keywords/Search Tags:Image Processing, hardware-software codesign, hardware acceleration
PDF Full Text Request
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