The Design Of Configurable Sigma-delta ADC With Wide Bandwidth And High Resolution

Faster and more efficient communication technologies bring more possibilities for applications and make people's lives more convenient.Along with this,the demand for high-bandwidth ADCs has increased correspondingly due to the widespread use of the signal-transmission process of the communication itself and the acquisition of content for communication.In fact,in addition to the pure bandwidth and accuracy requirements,the need for compatibility with different communication standards with different accuracy and bandwidth is also ubiquitous.Compared with the discrete-time sigma-delta ADC,the continuous-time sigma-delta ADC can achieve higher bandwidth,and is more suitable for processing medium and high-speed signals,while at the same time requiring accuracy.By configuring the decimation filter in the sigma-delta ADC,the output of different frequencies can be realized,and due to the characteristics of the pre-stage sigma-delta modulator,the output can be realized with different bandwidth and accuracy.These features make configurable continuous-time sigma-delta ADCs compatible with these requirements,and are of considerable value as an ADC solution that is compatible with the accuracy and bandwidth requirements of multiple communication standards including medium to high-speed signals.This paper presents a configurable continuous-time sigma-delta ADC design for the compatibility and bandwidth requirements of various communication standards including medium and high speed signals.The sigma-delta modulator portion of the sigma-delta ADC uses a 3-order feedback structure with a 4-bit quantized continuous-time sigma-delta modulator.The system was modeled at the system level and considered the non-idealities brought about by the integrator and feedback DAC.The circuit and layout design of the modulator,as well as the results of the post simulation,are given.The layout area of the modulator is about 1.8×2.0mm~2,and the signal-to-noise ratio of the modulator at 4MHz,1MHz and 250kHz bandwidth is74.26dB,101.03dB and 107.85dB,and the harmonic distortion is-118.1dB,corresponding to the noise of NBW=5859Hz.The bottom is about-140dB.The decimation filter portion of the sigma-delta ADC is designed as a decimation factor configurable decimation filter.The filter adopts a CIC filter,a CIC compensation filter and a half-band filter in a multi-stage cascade structure,wherein the decimation rate of the CIC filter is configurable.The decimation factor of the entire decimation filter can be configured to be 32,64,128,256,512.The system level design of each level of filter,the circuit structure and the layout design of the specific implementation are given.The passband ripple of the filter does not exceed 0.01 dB.The layout area of the filter is about 1.8×2.0mm~2,and the filtering function is correct.The modulator and decimation filter are combined into a configurable continuous-time sigma-delta ADC.The post-simulation results show that the signal-to-noise ratio of the ADC is 73.68dB,100.12dB and 107.09dB,respectively,at4MHz,1MHz and 250kHz bandwidth.The harmonic distortion is about-120dB,and the noise floor corresponding to NBW=5859Hz is about-140dB.The ADC can be configured to different bandwidth accuracy modes while meeting the corresponding bandwidth and accuracy requirements.