Design And Research Of A 12-Bit SAR ADC With Redundancy

With the development of modern digital signal processing(DSP)and computer technology,information processing is becoming more and more digital.Analog-to-Digital Converters(ADCs)are becoming increasingly important as key components for connecting analog and digital domains.Compared with other types of analog-to-digital converters,SAR ADC has great advantages in power consumption and area,so it is a research hotspot in the field of analog-to-digital conversion.Based on the 40 nm CMOS process,this article designs a 12-bit SAR ADC with a redundant bit.On the basis of ensuring the performance of the SAR ADC,metastable processing,offset calibration,and capacitance mismatch calibration are completed.The metastable detection circuit detects whether the comparator is in metastable state during normal operation of the ADC.When the comparator is in metastable state,the PN code is used as the comparator output,without waiting for the comparison result of the comparator,avoiding the missing codewords in low bits caused by metastable state.It improves ADC speed and performance.Unlike traditional binary weight structures,the SAR ADC of this design contains one redundant bit.This redundancy bit has a certain tolerance to the comparator comparison error and CDAC setup error in high bits,which can bring an improvement in ADC performance.Redundant bits are indispensable for the offset calibration and capacitance mismatch calibration of this design.For rail-to-rail input signals,redundant bits provide redundant codeword space.This design utilizes this redundant space to accommodate the offset voltage,and invents a new offset voltage calibration algorithm in conjunction with digital circuitry that reduces the offset voltage to less than 1LSB.Finally,the capacitive mismatch calibration is done in combination with the metastable and redundant bit design.The presence of a metastable state of the comparator is considered to be an "approximate quantization completion" of the input,thereby obtaining an ideal quantized codeword whose difference with the actual quantized code of the ADC is used to reflect the capacitance mismatch of the metastable bit.And the mismatch is subtracted from the output code during the actual working process of the ADC,that is,the capacitance mismatch correction is completed.The capacitance mismatch correction algorithm is implemented in combination with a digital circuit.The simulation result shows that the capacitance mismatch correction can improve the ENOB of 1.4 bits.The overall pre-circuit simulation results of the SAR ADC show that when the input is full-swing 40.14 MHz sinusoidal signal and the sampling frequency is 150 MHz,the ENOB is 11.86 bit,the power consumption is 9.27 mW,and the FOM is 17fJ/conversion-step.