Design And FPGA Implementation Of Key Technologies In The DVB-S2X Receiver

With the advent of the second-generation Digital Video Broadcasting（DVB-S2X）standard,the digital satellite broadcasting industry has opened a new page.Compared with the existing Digital Video Broadcasting Satellite Second Generation（DVB-S2）standard,the DVB-S2X standard has many advandages including higher spectral efficiency,greater access rate and more supported scenarioes.With the improvement of system performance,higher requirements are put forward for the implementation of receivers.In this thesis,we investigated the FPGA design and implementation of two key technologies in the DVB-S2X receivers,i.e.,the carrier recovery technology with large estimation range and the soft demapper compatible with all Amplitude and Phase Shift Keying（APSK）modulation types.The main contributions are:1)In order to ensure the anti-carrier frequency offset（CFO）performance of the receiver,we firstly analyzed the estimation range and estimation accuracy of various well-known carrier recovery algorithms,then we designed a FPGA implementation scheme for two carrier recovery algorithms-M&M algorithm and L&R algorithm.This scheme is applicable to all modulation modes in DVB-S2X standard by utilizing the pilots defined in its physical layer frame.Test results show that the design scheme can guarantee the normalized CFO estimation range of[-0.4,0.4]and the accuracy can reach 10^-3 under the low SNR environment with Es/No of-3dB.Meanwhile,the design module can work normally with a clock of 200MHz,and the download throughput rate can reach 200Msps.The Intellectual Property（IP）of the design module occupies the register,LUT and RAM resources,which are 2%,2%and 1%of the total resources included in the FPGA chip used,respectively.2)In order to be compatible with all modulation modes defined in DVB-S2X standard,the performance and implementation complexity of several state of the art soft demapping algorithms was firstly analyzed.A FPGA-based IP realization scheme of,the look-up-table-based soft demapping,was then designed and implemented.By simplifing the division of constellation mapping and optimizing the ROM table for storing constellation points related information,the designed IP can reduce the use of multipliers,comparators,and ROM resources in FPGA chip.Comprehensive and download test results show that the throughput rate of the designed IP can achieve the symbol rate as high as 108Msps with QPSK modulation.And its performance can approach the performance of the maximum likelihood algorithm.Furthermore,the soft demapping IP occupies 1%,2%and 3%of the total registers,LUTs and RAM blocks of the FPGA chip,respectively.