Design And Optimization Of FIR Filter Based On HLS Compiler

Field Programmable Gate Array(FPGA)adopts schematic diagram or hardware description language(HDL)for design input.Although FPGA can realize parallel pipeline operation,it requires advanced hardware to design skills during development,which is short of cycle length,difficulty and low efficiency.The latest development of High-Level synthesis(HLS)provides the ability to create FPGA computing accelerator completely with "C" code.The functions described by C/C++ are directly integrated into the register transfer level(RTL)code through the compiler,which greatly simplifies the process of design and debugging,reduces the difficulty of development,and realizes the automatic integration from software to hardware.The adoption of software design specifications can reduce hardware design cycles,improve performance,and expand the range of applications for which hardware efficiency advantages can be achieved.In this paper,the development history of HLS and development of domestic and foreign are comprehensively described,and the development status of advanced comprehensive and related HLS tools are introduced.High-Level synthesis has a general synthesis specification in the implementation design,and then a simple example is used to illustrate the integrated principle flow.In the field of digital signal processing,FPGA is an ideal platform for finite impulse response(FIR)filter design with its excellent performance.However,the traditional development method is difficult and it requires a lot of manpower and time.Advanced comprehensive fuzzy software to hardware design,therefore,this paper puts forward the design based on HLS FIR filter design ideas,using examples to illustrate the advantages of HLS-based design.Based on the idea of advanced synthesis,this paper mainly studies the Intel HLS compiler newly developed by Intel company.By designing and implementing a FIR filter,it introduces its environment configuration,operation and compilation methods in detail,and demonstrates the powerful functions of Intel HLS compiler.Again by DSP and FPGA realization of filter,the two methods and advanced integrated design,this paper compares and analyzes,according to the results of FIR filter is designed based on HLS from digital system abstract norms,seeking to achieve a given behavior register transport layer,rapid realization of function module architecture,speed up the validation,make up for the inadequacy of hardware design.By designing the filter,advanced hardware on the road to solve the software is the most difficult problems,however,the charm of high-level synthesis is far more than these,Intel HLS development tool configuration of various optimizations are more likely to improve the quality of design,due to the filter tend to have "can explore the" memory architecture,including loop unrolling and pipe using makes its can be optimized based on HLS.Furthermore,this paper makes further optimization according to the memory architecture characteristics of the filter based on the optimization strategy of the Intel HLS compiler.Five optimization methods,including loop optimization and precision optimization,are used to compare and analyze the obtained optimization results.In conclusion,in specific occasions,it can reasonably and flexibly use the mixture of various optimization methods,remove the code redundancy as much as possible,design a reasonable data transmission strategy,fully optimize access storage,and make use of as many resources as possible,so as to finally achieve the relative optimal implementation of HLS design algorithm.