LPDDR4 Error Checking And Correction Circuit Design And Static Timing Analysis

With the increasing speed of electronic devices processors,the speed of data processing in mobile terminals should also be increased accordingly.The stability of data should be guaranteed while ensuring high-speed operation,LPDDR4-SDRAM(Low Power Double Data Rate SDRAM)with ECC(Error checking and Correction)function can correct error data bit without interrupting the current running state,which improving the stability of memory effectively.With the rapid development of the digital integrated circuits,the timing convergence of critical path has become an important criterion for the normal operation of circuits.The advantages of Static Timing Analysis covering almost 100% of circuits are becoming more and more important.It can accurately find critical path.Especially when chip design enters deep sub-micron level,On Chip Variation and Signal Integrity have become influencing factors which must be taken into account during Static Timing Analysis.The research content of this paper comes from a memory chip design project of Micron Semiconductor for mobile communication terminal.Aiming at ECC block in LPDDR4-SDRAM chip with memory 2133 MHz of frequency and voltage is 1v,based on the method of Full Custom design for timing analysis and optimization of ECC block during Read,Write and Mask write operation,and through Verilog build a test bench.On the basis of the optimization of ECC algorithm,the circuit structure changes accordingly,which requires a higher understanding of the circuit.It is difficult to write the correct constraints.Aiming at the change of circuit structure,this paper proposes a scheme of data acquisition based on data flip,and builds a test platform to accurately collect simulation data.The main work of this paper includes:Firstly,analysis the timing feature of Read,Write and Mask write opeartion of LPDDR4-SDRAM,and based on the Read,Write and Mask write paths of ECC block,a single bit and multi bits static timing analysis scheme for ECC block are proposed.Secondly,static timing analysis of ECC module based on full custom design circuit LPDDR4-SDRAM is completed by Prime Time platform of Synopsys.In order to get accurate timing information of critical path,a test platform was built by writing Verilog based on the analysis of critical path timing report on the premise of completing static timing analysis and all paths met.Finally,based on the test platform,three kinds of operation patterns are compiled for dynamic simulation.By grabbing the data passing through the critical path and data flipping consistent with the report as the input data of LPDDR4-SDRAM,the data information of read-write and masking-write operations can be obtained respectively.The test results show that the ECC module designed and optimized in this paper can correct 1 bit error code of 128 bit data,and the multi-bit error code can be corrected by optimizing the algorithm.Write operation test results show that:(1)the transmission time of data in the encoding circuit is 957ps;(2)the setup time is 404ps;all meet the design requirements of less than 1ns.The mask write operation test results show that:(1)the transmission time of data in the critical path for the decoding circuit is 849ps;(2)the establishment time of latch transmission data in internal read operation is 842ps;(3)the establishment time of latch transmission data in internal write operation is 494ps;all meet the design requirements of less than 1 ns.The test results of read operation show that:(1)the reading time of the encoding circuit is 936 ps;(2)the setup time of the latch transmission check code is 415 ps;(3)the time of the three-state gate transmission data is 398 ps;all meet the design requirements of less than 1 ns.