Design And Implementation Of Self-erasing Module For Programming Memory And Long-line Transmission

The acquisition memory in this paper is mainly used for the acquisition and stora-ge of the working parameters of an aircraft,and the data can be read back afterward s to obtain and analyze the flight data.According to the demand of a project,this pap-er designs a self-erase module on the acquisition memory.When in a special situation,this module can respond to the self-erase instruction reliably,and can complete the d-ata erasation within a short time under the reliable power supply of the battery.In addition,after considering the usage environment,in order to ensure the reliability of the data read back,the data transmission design is also carried out.Finally,a test platf-orm is built to conduct closed-loop test on the two-part design to ensure the reliable implementation of the design.This paper introduces the significance of the design of the self-erase module and the long line transmission of the acquisition and editing memory and the research status of related technologies.Then,according to the functional requirements and technical indexes of the relevant parts of the acquisition memory,the technical requirements of the self-erase module and the long-line transmission module are analyzed,and the de-sign schemes are given.Then the design is explained in detail.Among them,in view o-f the phenomenon of misjudgment which is easy to be interfered when the selferase i-nstruction is judged,the receiving interface is designed to resist interference on the h-ardware.In terms of logic,the voting logic is used to judge the continuous level type self-erase instruction based on FPGA,and the fault-tolerant logic to judge the continuous pulse self-erase instruction is designed.Aiming at the problem of power supply re-liability of self-erasure module,scientific battery management is realized through the design,and reliable conversion of main and standby power supply is made to ensure t-he reliable power supply during the self-erasure process.Aiming at the problem of error code in high-speed data transmission,software logic is the focus.CRC code error detection and ARQ error correction optimization methods are adopted to improve the r-eliability of data based on FPGA.At last,this paper conducted relevant tests on the design by building a test platform,and the test results showed that the functions of the design and relevant technical indicators were in line with the expectation,the module was stable and met the task requirements.