Design And Verification Of QDR SRAM Memory

With the development of the electronics industry,the demand for high-bandwidth memory is growing rapidly.For high-speed(data rates higher than 200 MHz)network routers,hubs,and switches,current memory standards are becoming bottlenecks.This requires high performance,high speed,and large capacity memory.QDR SRAM(Quadruple Rate Static Memory)is the ideal processor for high-speed,high-bandwidth operation,while also taking into account different performance.Compared to traditional SRAM(static memory),QDR SRAM(four times rate static memory)is faster and has higher throughput,so studying QDR SRAM is very important for the memory industry.At present,the products of foreign QDR SRAM series have been developed to the 4th generation,processing data faster and capacity is larger,can meet the speed of information exchange of modern communication,and the domestic related industry is just in its infancy,yet Similar products.This topic is a memory product research project originated from the enterprise.The technical specifications of the QDR SRAM designed and designed by the project are: compatible with 1MX36 and 2MX36 configurations;read and write operations have independent read and write ports,which do not affect each other.;read and write ports are DDR interface;2.5 clock cycle read latency,1 clock cycle write latency;4 word burst function and compatible with 2 word burst function;dual clock control address and control signal;QVLD Accurate sampling for reading data.The paper is based on technical indicators,and the specific work arrangements are as follows:The paper firstly studies and determines the overall architecture of QDR SRAM,and carries out detailed analysis of each functional module(DLL module,IO module,storage array module,JTAG module).In the design of the memory array,for the problem of different time in the process of control signal transmission,this paper proposes a symmetric storage array to ensure the same path of the control signal to the storage unit.At the same time,a method is proposed and adopted.A two-stage cache structure is used in the data and storage array to solve the problem of delay of IO(input and output port)and delay in place and route.The read and write logic module and the JTAG module are two important modules in the QDR SRAM.After completing the overall architecture of the QDR SRAM and the analysis of each functional module,this paper adopts a bottom-up design method,and the two modules are designed in detail..Then use the black box verification method to verify the function of the module based on the verification platform built by SV language.The JTAG module verification shows that the functional verification of the 11 chains that make up the module is all correct and meets the design requirements,indicating that the JTAG design is correct.The read and write logic module verification shows that the designed chip can be successfully written into the memory array in the burst4 mode and can be successfully read in the burst4 mode.The timing also meets the design requirements,indicating that the design of the read/write module is correct.Based on the completion of two important module read and write logic modules and JTAG module design,all modules are integrated for verification,and the verification results show that they meet the design requirements.