Design And Implementation Of Firmware Converting SAS To PCIe

The SAS(Serial Attached SCSI)interface has matured its applications in the enterprise due to its high performance and high scalability,and has its own complete ecosystem,so it is still the main storage interface of current servers.The development of 5G has brought a large amount of data,which has led to a sharp increase in the demand for storage capacity.Especially for enterprises,servers need larger capacity storage devices to support these data.At present,the SAS SSD with the same capacity are more expensive than the PCIe SSD.Therefore,in the research of this project,consider the use of an intermediate medium to achieve the purpose of retaining the SAS interface with a stronger ecosystem and reducing enterprise storage costs.Specifically,the PHOENIX LQFP208 chip independently developed by Sage Microelectronics Corp.is used as the hardware platform to connect the enterprise server and the PCIe SSD respectively.By using the firmware designed in this dissertation to control the chip work,the basic purpose of reading and writing PCIe SSD data by the enterprise server is achieved.Just like the translator,the firmware designed in this article must have the function of identifying the two interface protocols of PCIe and SAS,and then based on this,control the coordination of internal key modules by setting the relevant registers of the modules used inside the chip.Therefore,the read and write tasks transmitted from the server with the SAS interface as the storage interface can be executed in the PCIe SSD.In this firmware,since two processors are used to manage the transactions on the SAS target side and the PCIe host side,two independent firmware projects are designed to handle the SAS and PCIe side transactions,respectively.In addition,because SCSI has other command types in addition to the data read and write commands,the PCIe side only needs to process the data read and write commands.Therefore,the design reads and writes the commands of the PCIe SSD data in a separate register for the PCIe side to directly Take out the command to save the time lost in querying the read and write commands.In addition,in this firmware,it is also designed to store data and commands in different memories,in order to quickly process data or commands and reduce delay.Before the design of the firmware,this dissertation first analyzes the development background and current situation of computer interfaces,and then introduces the theoretical knowledge of the concepts and working principles of SAS and PCIe interfaces.After fully understanding and understanding these two interface technologies,we will enter the core partof the thesis,which is firmware design.In the firmware design,the overall design to the writing of the code is introduced and analyzed,and the necessary program flow is explained in more detail.After completing the firmware design,enter the final debugging stage.During the debugging process,on the one hand,a low-speed debugging method is used,that is,the Universal Asynchronous Receiver / Transmitter(Uart)prints the marks in the code to make it easier to find code vulnerabilities,and on the other hand,transition from partial debugging to Overall debugging,that is,at the beginning of debugging,the firmware responsible for SAS side transactions and PCIe side transactions are burned to the chip respectively,and separate on-board debugging verification and optimization are performed.After successful debugging,two copies of firmware are downloaded to the chip And connect the server and PCIe SSD for overall debugging.Experiments show that the firmware designed in this subject can achieve basic read and write functions,and has good reliability and speed.At the end of the thesis,the research contents are summarized and prospected.