Design Of Anti-radiation Agile Development Platform Based On RISCV Processor

With the development of the Internet of Things and the rise of artificial intelligence,the demand for chips has become more and more diverse.The traditional chip development model has a long design cycle and high investment risk.These factors seriously affect the development of the chip.The use of more agile development methods has become the most important demand for chip development in the new era.The same problem exists in the development of anti-irradiation chips that have extremely high reliability requirements.The introduction of agile chip development methods into the design of anti-irradiation chips has accelerated the development of radiation-resistant chips,which is of great significance to the development of my country's aerospace industry and nuclear physics.This dissertation designs an anti-irradiation reinforcement agile development platform based on FIRRTL(Flexible Intermediate Representation for RTL)based on the in-depth research on chip agile development methods.The platform includes three parts: front end,intermediate conversion and back end.The front end is used to parse the hardware description files in Chisel format and FIRRTL format,and the hardware description after parsing is passed to the intermediate conversion part in the form of an abstract syntax tree.The intermediate conversion embeds the local triple modular redundancy(Local TMR)reinforcement algorithm and the distributed triple modular redundancy(Distributed TMR)reinforcement algorithm based on SCC(Strongly Connected Compoent),which is used to strengthen the triple modular redundancy of the input circuit.The back-end part converts the hardware description after the triple modular redundancy into a Verilog description by calling the Verilog generator in the FIRRTL framework.Use Scala language to develop all parts of the platform.The circuit module described by Chisel HDL and FIRRTL is used as the input of the platform for processing,and a Verilog file with triple modular redundancy description is obtained.The hardware described by Chisel HDL and the hardware described by FIRRTL are converted into Verilog file descriptions.The original Verilog files and Verilog files with triple modular redundancy descriptions are simulated and compared using VCS simulation tools to verify the correctness of the platform functions.Use the error injection tool to inject error into the generated Verilog file to verify that the file generated by the platform has the function of resist Single-Event Upsets.Build the minimum system of RISCV processor,test the RISCV processor processed by the platform,and verify that the platform has the ability to strengthen the RISCV processor with triple modular redundancy.