Optimal Design Of Multi-core Heterogeneous Processors For High-density Computing Applications

In the fields of nuclear magnetic resonance,radar imaging,large data analysis and other applications,data processing has the characteristics of large computational load,large data throughput,high real-time requirements,and puts forward higher requirements for the processor's computing ability,parallelism,and data throughput.Currently,most of these tasks are performed on general purposed processors or Application-specific integrated circuit.Application-specific integrated circuit are chips customized for a specific task,which have very high performance,but their functions are very limited and they can only perform specific tasks.general purposed processors are software-based computing tasks that are difficult to meet the application requirements in large data and high real-time scenarios.With a single chip integrated density of more than 1 billion transistors,a small-core,large-array,coarse-grained,reconfigurable multicore processor architecture between a general-purpose processor and a dedicated chip is becoming the mainstream architecture for high-density computing.This architecture provides T-level computing power with hundreds of computing units,provides high parallel and high bandwidth data interaction between computing units using high-performance on-chip networks,and customizes the function of computing units and the data flow direction between them using reconfigurable computing technology to achieve a high degree of alignment between algorithms and structures.Based on the above background,the project group has completed the optimal design of the heterogeneous multicore processor HMCS(Heterogeneous Multicore Computing System),and completed the improved design and implementation of the heterogeneous multicore processor HMCS-II.The main work of this paper is as follows:Firstly,the working mechanism of each level in the system is standardized,including the top-level working mechanism of the master,the behavior of operation nodes,the behavior of data transmission on the network on the chip,as well as the data storage format and data description method,which effectively improves the scalability of the whole machine.Secondly,the internal key module design of HMCS-II system has been improved,including the main controller instruction set and the main controller core,the network on chip and its interfaces,and the multi-channel external memory access interface.Thirdly,the system integration of HMCS-II chips is completed,and all the back-end work is done on the field bus chips,and the whole system hardware prototype development for loading real applications is completed.Finally,the validation test environment is set up,the application software assisted programming environment and debugging environment are designed,some typical algorithms are tested for programming load,HMCS-II is evaluated for function and performance,and the correctness and architecture advantages of the design are verified.