Research And Design Of A Track And Hold Circuit With 8GHz Bandwidth

With the rapid development of high sample-rate analog-to-digital converters(ADC),time-interleaved ADC has become a research hotpots.Track and hold circuit is a key circuit of ADC that determines the bandwidth,conversion rate and conversion accuracy of analog-to-digital converters.A track and hold circuit with 8GHz bandwidth for 8 bit 10GSPS time-interleaved ADC in a 65nm CMOS process is designed in this thesis.After systematically analyzing track and hold circuit and the non-ideal factors,a track and hold circuit is designed with improving measurements.Three-stage hierarchical track and hold is adopted to realize high bandwidth and to mitigate timing.The dummy switches,which are cross-coupled with the sampling switches,are used to compensate for signal feed-through in the design of bootstrap switches.To improve linearity,bandwidth,and settling speed,a current feedback loop is applied in source follower,it was used as the first and second stage buffers.By adding source degradation resistance into the designed cascode buffer,its linearity is greatly improved,and it is used as the third stage buffer to amplify the sampling signal compressed by pre-stage.The simulation of the circuit shows that the bandwidth of the track and hold is larger than 10.96GHz,the SNDR is higher than 47.91d B and the SFDR is higher than 48.47d B in the bandwidth range.The layout design is done and post-simulation of the circuit is completed.The non-ideal factors in layout design and the corresponding optimization measures are considered during the design process.The area of the layout is 3.69mm~2.The post-simulation shows the bandwidth is larger than 8.85GHz,the SNDR is larger than 44.60d B and the SFDR is higher than 45.87d B in the bandwidth range,which can meet the requirements of the circuit.