Study On Signal Equalization Technology At The Receiver Of High-Speed SerDes Communication Systems

In SerDes high-speed serial communication system,the inherent loss of the channel and various non-ideal characteristics,such as reflection,crosstalk and jitter,become more and more serious with the increase of transmission rate,which triggers the Inter-Symbol Interference,furthermore leads to the decline of the overall performance of the link.Therefore,it is particularly important to apply equalization technology to SerDes high-speed links.In this paper,a signal equalization scheme applied to SerDes system is proposed,the design of equalizer chip applied to SerDes receiver is further completed.The main work of this paper as follows:1.The equalization techniques are discussed,which are introduced to solve the problem of signal integrity in high-speed link.After analyzing the principles and performance characteristics of the feedforward equalizer used in the transmitter,continuous time linear equalizer and decision feedback equalizer used in the receiver of SerDes communication system,a high-speed SerDes link which includes equalization module is furtherly built,the optimal equalization structure is obtained by means of adjusting the parameters of the equalizer.2.Based on the system simulation results of SerDes link model,the equalizer circuit design applied to the high-speed SerDes link receiver is completed,which adopts the joint equalization structure of linear equalizer and decision feedback equalizer.In the design of linear equalizer,multi-stage circuit cascade structure is adopted,in which the first-stage variable gain amplifier provides variable DC gain for the signal at the receiver,which compensates the low frequency loss of the channel.In the design of the second-stage continuous time linear equalizer,based on the traditional structure,active inductance circuit and negative capacitance circuit are further adopted to expand the equalizer bandwidth and compensate the high-frequency loss of the channel.In the design of decision feedback equalizer,half-rate structure and speculative tap are used to solve the timing limitation of traditional decision feedback equalizer structure in high-speed signal equalization.3.Based on the pre-simulation design of equalizer circuit,the post-simulation layout and chip mode layout of the circuit are completed based on TSMC 65 nm process,in which the post-simulation layout of the core circuit occupies an area of 0.005 mm~2.The post-simulation results show that for the 25 Gb/s pseudo-random sequence signal passing through the 12-inch FR-4 backplane channel,the equalizer can effectively eliminate the inter-symbol crosstalk and improve the eye opening of the signal at the receiver.In conclusion,the joint equalization structure proposed in this paper provides a feasible solution to the signal equalization problem in SerDes system,at the same time providing design guidance for high-speed link receiver chips,which has certain reference value in academic research and production application.