Research And Implementation Of The 127Gbps DP-QPSK Signal Synthetical Processing Technology

With the rapid development of cable communication technology,the bandwidth of cable signal is growing.Meanwhile,speed of signal transformation is becoming more critical.At present,the bandwidth of major cable signal communication company is 127 Gbps which is gradually expanding to 400 Gbps and even 1Tbps.Present transformation technology could hardly meet today's needs.Developing effective technology to reach the maximum transformation capability highlights researchers' goal.To fullfil the needs of high speed signal transformation,traditional modulation modes,such as OOK and DQPSK are gradually developing to base on Polarization technology QPSK,and high order QAM modulation is under development.Meanwhile,new transformation needs set new requirements for dispersion compensation,ultra high speed digital domain equalization technology,ultra high speed sampling and digital coherent receive.Besides,high speed transformation system is often based of forward error correction coding and multi-step coding,which is especially complicated when soft LDPC and massive step BCH,and RS coding are weaved together.To decode high speed cable signal data,it is a must to recognize such code and weaving format.Error correction is impossible without multiple iterations.Good correction is the result of multiple iterations.The application of such technology raise great challenge for the communication signal detection.This paper focuses on the research and implementation of the 127 Gbps DP-QPSK signal synthetical processing technology.Firstly,based on the transmission theory of 127 Gbps DP-QPSK signal,the author analysed signal format and property,then briefly introduced the overall theory construction which focues on system hardward design plan.The author also gave a discussion on critical technoly such as Polarization technology,ultra high speed digital domain equalization technology,frequency-offset estimation,electronic dispersion compensation and nonlinear damping,soft decision LDPC,and the transmission of ultra high speed parallel signal.Secondly,the author introduced system processing module which focuses on flow processing mode and error correction.This paper had a full discussion on signal synchronization,weaving transformation,decoding of error correction signal and format transformation.Then,this paper presents detailed high speed signal real-time processing plan which is based on massive FPGA.In conclusion,this paper gave an achieveable engineering plan for standardized output.After a test,the pater presented the results of multiple test of various variable property to verify the effectiveness of the plan presented in this pater.