FPGA Design And Experimental Verification Of Intermediate Frequency Offset Module Of High-speed Spatial QPSK Coherent Optical Communication Receiver

With the increasing demand for bandwidth,people have higher and higher requirements for speed and capacity in communication.Coherent optical communication system has become the mainstream of space communication because of its large receiver capacity and long relay distance.Because of the difference between optical fiber channel and space channel,Digital Signal Processing(DSP)technology in optical fiber communication cannot be completely applied to space channel.At the same time,due to the inconsistency of laser frequency between sender and receiver,the signal at receiver is introduced into a cumulative phase error,which accumulates more and more with time.Therefore,it is important and difficult to remove the phase error caused by frequency offset accurately in spatial channel DSP algorithm.In the process of hardware implementation,how to design and optimize the parallel frequency offset estimation algorithm with low complexity,accurate frequency offset estimation and high speed has always been a key problem in hardware implementation.In this paper,Quadrature Phase Shift Keying(QPSK)system for coherent optical communication at 2.5GBaud symbol rate,The parallel optimization design and parallel hardware implementation of Field Programmable Gate Array(FPGA)are carried out for frequency offset estimation algorithm.The main research contents are as follows:(1)In 2.5GBaud QPSK system,aiming at the problem of multiple ofπ/2 of phase rotation of output signal in hardware implementation of the classical parallel fourth power estimation algorithm in the frequency offset estimation algorithm of coherent receiver,the timing phase ambiguity elimination frequency offset estimation algorithm is proposed.Through the hardware optimization of Park algorithm,a frame synchronization sequence with a cost of 0.384%was introduced,and a parallel timing phase ambiguity elimination frequency offset estimation algorithm was designed and implemented for hardware system.The key parameters of the algorithm were determined by simulation.The space optical communication channel is simulated by the simulation platform,and the parallel algorithm is verified by off-line experiment under the conditions of 15.91dBm transmitting optical power,-38dBm receiving optical power and 10km transmission distance.The bit error rate of the system is less than 5×10-5.The parallel algorithm is verified by building an indoor FSO channel,and the verification results show that the optical power of the system can reach-31 dBm when the system bit error rate is less than 5×10-5.(2)In the 2.5GBaud QPSK system,aiming at the problem that the parallel-timing estimation algorithm and the classical parallel fourth power estimation algorithm enlarge the noise four times in principle and occupy more hardware resources in hardware implementation,a training sequence with the cost of 1.538%is introduced,and a parallel frequency offset estimation algorithm based on training sequence was designed and implemented for hardware system.It has been verified that the actual estimation range of the parallel frequency offset estimation algorithm based on training sequence is expanded to[-12.5GHz,12.5GHz].When the system frequency offset is 300MHz,the order of magnitude of bias estimation accuracy is 0.1MHz,which is an order of magnitude higher than 3MHz required by the experimental project.Compared with the timing phase ambiguity elimination frequency offset estimation algorithm,the logical resource is reduced by 9%,which effectively improves the algorithm accuracy and reduces the hardware resource usage.The space optical communication channel is simulated by the simulation platform,and the parallel algorithm is verified by off-line experiment under the conditions of 15.91 dBm transmitting optical power,-38dBm receiving optical power and 10km transmission distance.The bit error rate of the system is less than 5×10-5.The parallel algorithm is verified by building an indoor FSO channel,and the verification results show that the optical power of the system can reach-33dBm when the system bit error rate is less than 5×10-5.