Research On A Key Technology Of Multi-Rate LDPC Coding And Decoding

LDPC codes have become one of the current mainstream channel coding schemes due to their excellent error correction performance,and are used in numerous communication systems.In time-varying channels,it is generally required that the code rate of the LDPC code can be flexibly adjusted according to the current channel state,so multi-rate are required.This article focuses on the key technologies of multi-rate LDPC coding and decoding.The main contents are as follows:First,a multi-rate coding and decoding scheme for QC-LDPC codes is designed.Generally,in order to obtain multi-rate,a variety of different check matrices can be used,and techniques such as puncturing,shortening,and expanding can also be used.The scheme designed in this paper combines matrix switching with puncturing technology.Multi-rate coding consists of a generator matrix configurable encoders and puncturing modules.Multi-rate decoding is composed of a filler module and a parity check matrix configurable decoder.Second,the proposed multi-rate coding and decoding scheme is designed and simulated.Firstly,the characteristics of commonly used coding algorithms are analyzed,and QC-LDPC code generator matrix coding algorithm is used to design a configurable encoder.Then the puncturing algorithm is analyzed,and the Grouping and Sorting algorithm is used as the puncturing algorithm.Then compare different decoding algorithms,choose the layered normalized min-sum algorithm for configurable decoder design.Finally,the LDPC code in IEEE 802.16 e is used to simulate the decoding algorithm and puncturing scheme.The simulation of the decoding algorithm verifies the superiority of the layered normalization algorithm.At the same time,the normalization factor ? is determined to be 0.75,the maximum number of iterations is 10,and the quantization bit width is 6 bits.The simulation results of the puncturing scheme show that the use of parity check matrix with code rate 1/2 and 3/4 combined with puncturing to achieve the 4 code rates in the protocol compared to the use of 4 parity check matrix brings a performance loss within 0.15 dB.The benefits are that it can save matrix storage resources and easily obtain new code rates.Third,the FPGA implementation of the multi-rate coding and decoding scheme was completed.Encoder and decoder supporting the four code rates defined in IEEE 802.16 e protocol are designed.The overall structure of the codec and the specific implementation of key modules are given.RTL code writing,behavior-level simulation and synthesis were completed..The synthesis results shows that the hardware resources consumed by the multi-rate codec are saved 50% compared to the independent single-rate codec.The multi-rate coding and decoding scheme proposed in this paper is universal to some extent and can be used in communication systems which need to support multi-rate LDPC coding and decoding.