10Bit Single-ended Input Successive Approximation Register ADC

Successive approximation analog-to-digital converter(SAR ADC)is hugely attractive in wireless sensor networks and biomedical devices due to the excellent operating efficiency and speed.First,the switching capacitor circuit architecture of SAR ADC is compatible with CMOS integrated circuit process,which is beneficial to reduce cost.Next,operational amplifier is not needed greatly reduces power consumption.,which is perfect for low power battery-powered application.In addition,the matching of capacitance has been effectively improved and the size of the smallest unit capacitance has been greatly reduced due to the improvement of technology in the world,which improv the performance of circuit.In this paper,a single-ended SAR ADC with input architecture was proposed.Compared with the traditional differential input architecture,DAC sampling signal is not needed in this architecture and the input capacitance of the circuit is reduced by nearly 80%,which reduce the requirement for the driving capability of the previous circuit.In order to ensure that simple and low-power operation can be performed with sufficient bandwidth,the bootstrap technology is used in the sample-hold circuit.The sampling signal is the input to one side of the comparator and that to the other side is the DAC following signal.PMOS and NMOS differential input pairs is used in the static latch comparator to provide a rail-to-rail input range and the kick back noise is diminished through a current mirror between the preamplifier stage and the latch comparator.DAC binary weighted capacitor array is composed of MIM capacitors.Because the minimum unit capacitance is not limited by KT/C thermal noise,the capacitance value of the unit capacitance is set to 15 fF based on the process design rules.The overall designation of circuit in this study was under the relevant design environment of the Cadence platform and the the 0.18 um 1P6M CMOS process was employed.Besides,Matlab was also used to analyze data and parameters.The simulation results indicate that the performance of the SAR ADC is ENOB = 9.33 bit,SNR = 58.9dB,SFDR = 68.0dB,the power consumption of analog circuit is 874.17 uw,and that of digital circuit is 4.228 mW under the conditions where the analog power supply voltage is 3.3V,the digital power supply voltage is 1.8V,and the sampling rate is 1Ms/s.