Optimal Design Of Key Circuits For Voice Activity Detection

With the development of the IoT,the technology of speech recognition has received more and more attention.As an important module in speech recognition,Voice activity detection directly affect the accuracy and speed of speech recognition.Time-frequency voice activity detection is widely used in hardware implementations of voice activity detection because of its anti-noise and real-time performance.An optimized time-frequency endpoint detection hardware implementation with accuracy,which has higher computing speed and less cost of hardware resources,is designed in this thesis.Firstly,the key modules of the voice activity detection circuit are determined by software simulation of time-frequency VAD: frame division module and spectral entropy calculation module.In order to reduce the cost of hardware resources in the frame circuit,a structure of first computing and then storing is proposed,which replaces the original structure of first storing and then computing.In order to reduce the delay of spectral entropy calculation circuit,a pipelined spectral entropy calculation circuit is proposed.On the one hand,the design of FFT unit which consumes more time is designed in pipeline structure,on the other hand,the data dependence relationship between each step in the calculation of spectral entropy is removed by the conversion of the calculation process.So that the calculation of spectral entropy can be designed as a pipeline structure.ISE tools are used to verify the VAD circuit on the FPGA board with Xilinx Artix-7 chip.The experimental results show that the VAD circuit designed in this thesis can achieve more than 90% detection accuracy when the SNR is 0 dB;The calculation delay is reduced by 18% compared with similar EZV-EDG VAD circuit,and the maximum frequency is 130.730 MHz;The hardware resources of register and LUT are reduced by more than 10% compared with DoV VAD circuit and spectrum subtraction VAD circuit.The results show that a hardware circuit implementation with high noise resistance and computational efficiency but less hardware resource is designed in this thesis.