Design And Application Of Majority Gate Based On QCA

With the rapid development of the microelectronics industry,the feature size of transistor keeps shrinking.Nowadays the semiconductor technology has entered deep submicron era,reducing the feature size of silicon-based CMOS devices become more difficult.In order to reduce the size of integrated circuits and enhance their performance,the microelectronics industry has focused on nanotechnology with higher integration and better performance.Among many nano-devices,Quantum-Dot Cellular Automata(QCA)is one of the most promising technologies to replace traditional CMOS.Previous researchers only used three-input Majority gates and inverters as basic gate circuit units to design QCA circuits.But if the five-input Majority gate is applied in the design,the performance of the circuit will be improved.Therefore,the design and application of the five-input Majority gate has aroused extensive interest of researchers.This paper mainly studies the design of a five-input Majority gate circuit composed of three circuit layers based on QCA,drawing on the experience of previous QCA circuit design.By using proposed five-input majority gate,several basic circuit units are designed.The paper mainly consists of the following parts:1.The structure,principle and model of QCA devices are studied.Several basic gate structures of QCA circuits are analyzed.A design of five-input Majority gate based on three-layer circuit is proposed and applied to SR latches.2.Based on the sutdy of MI(Majority-Inverter)logic,a full adder is designed by using the proposed five-input Majority gate,and it is used in adders up to 64 bits.Next the carry delay multiplier based on FIR filter network is analyzed and the proposed full adder designed is applied to the multiplier.Compared with the previous design,it shows that the area and QCA cells are obviously reduced.The QCA cells and area of the adder can be improved up to 43% and 87.2%,and the QCA cells and area of the multiplier can be improved up to 48.2% and 100%.3.By analyzing the previous comparators,a comparator using the five-input majority gate is proposed,the delay of the proposed comparator has been significantly reduced.The proposed comparator can be expand up to 8 bits,and the simulation shows it works correctly and the delay is lower than that of the previous comparator design,and the delay of the proposed comparator will not increase linearly with the bite size.