| Fibre Channel(FC)switches are the core devices of storage area networks and avionics networks.The key technologies include: data queuing structure,switching structure,and scheduling algorithms.The data traffic in the storage area network is very large.The traditional Internet protocol cannot meet the requirements for fast transmission of large amounts of data.The FC protocol has the characteristics of low latency,high rate,and strong anti-interference ability,which can support mass data transmission.The avionics network has very high requirements for data real-time,bandwidth,and reliability,and the FC protocol can meet the usage requirements.The FC switch is based on the FC protocol.As the core device of the FC network,FC switch directly determines the performance of the storage area network and avionics network.This thesis will focus on the three key technologies of the FC switch.Based on the horizontal subject of a domestic research institute,the data queuing structure,switching structure,and scheduling algorithm were studied in depth for their impact on the performance of FC switches such as latency,throughput,fairness,and bandwidth utilization.Based on a large number of theoretical studies,the existing VOQ data queuing structure and iSLIP scheduling algorithm were improved,and a high-performance,large-capacity 48-port FC switch was designed and implemented based on a single FPGA.After functional simulation and experimental verification,the switch functions normally and its performance is improved compared to conventional switches,providing a technical basis for the subsequent implementation of application specific integrated circuits(ASIC).The main work and innovations of the thesis are as follows:(1)The hierarchical structure,data frame format,flow control strategy,protocol service type,and topology of the FC protocol are studied to provide a theoretical basis for designing FC switches.(2)The common switching structure of FC switches is studied to select a mature and stable switching structure for the switches in this thesis,such as Crossbar structure.(3)The working principles,advantages and disadvantages of the currently used data queuing structures such as input queuing,output queuing,joint input-output queuing and virtual output queuing(VOQ)are thoroughly researched.Aiming at the problem of low buffer utilization of the most widely used VOQ structure,this thesis proposes A VOQ structure based on shared cache.The actual results show that this structure can significantly improve the cache utilization in the switch.(4)The iterative matching process of PIM scheduling algorithm,RRM scheduling algorithm,iSLIP scheduling algorithm and the performance of each algorithm are studied in depth.Aiming at the problem of reducing the bandwidth utilization of the switch due to pointer synchronization of iSLIP algorithm,a method based on Improved iSLIP scheduling algorithm based on association pointer.Experiments show that when the load is greater than 93%,the bandwidth utilization of the algorithm in this thesis is significantly higher than the conventional iSLIP algorithm.(5)Based on the data queuing structure and scheduling algorithm proposed in this thesis,a 48-port switch is designed and functional simulation is performed using Modelsim software.After the functional simulation is completed,the hardware platform is built using FPGA and embedded processor,and the JDSU Xgig protocol analyzer is used to test the switch system function and performance.The simulation and experimental results show that the 48-port FC switch designed in this thesis functions normally.Under the premise of the same hardware cost,the performance such as throughput and delay are better than the conventional switch. |
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