Research And Implementation Of Hardware Acceleration Of Convolutional Neural Network Based On ZYNQ

Convolutional neural networks are an important research direction in the field of artificial intelligence.Because of its unique network structure,it is especially good at video image processing.It improves the problem of too many parameters of the traditional algorithm in the field of image processing through the unique methods such as local perception and weight sharing.However,due to the convolutional nature of convolutional neural networks,a large number of convolution operations are still needed in the image processing process.This massive operation makes the network running speed severely constrained,affecting the convolutional neural network in real-time,small embedded The application in the system.Therefore,the accelerated design of convolutional neural networks has become one of the hot research directions.Based on the structural characteristics of convolutional neural network model and the heterogeneous structural advantages of ARM+FPGA of ZYNQ chip,this paper re-analyzes the feasibility of parallel implementation of convolutional neural network model in ZYNQ from two aspects: software implementation and hardware acceleration.A hardware acceleration system based on ZYNQ platform for convolutional neural network is designed,and the image classification and recognition function based on CIFAR-10 data set is realized.In order to improve the running speed of convolutional neural network on ZYNQ platform in this system,this paper adopts a PL-end of ZYNQ,ie FPGA,to realize the acceleration scheme of convolutional neural network with hardware circuit.However,due to the limited hardware logic resources of the PL end of the ZYNQ platform,it is impossible to implement a complete convolutional neural network by means of hardware circuits.Therefore,only the convolution operation function is integrated into the PL end and accelerated by hardware circuits.In this paper,the model structure of the convolutional neural network is analyzed in detail,and the algorithm principle and calculation formula of the key layer in the model are given.Then use the Vivado tool and Verilog language to design the image preprocessing IP core,etc.,and complete the construction of the system hardware engineering.On the basis of completing the hardware engineering construction,referring to the classical network model Le Net-5,a convolutional neural network model with relatively simple structure is designed for the limited resources of ZYNQ platform.Then use the SDx tool to implement the convolutional neural network using the C language software on the built hardware platform.On the basis of the software implementation of the convolutional neural network,the software source code of the convolution layer is analyzed in detail.On the theoretical level,the key part of the convolutional neural network that limits the running speed of the convolutional neural network is found,and the correctness of the theoretical analysis is verified by experiments using the SDx tool.Then,through the SDx tool,the accelerating method such as pipelined,loop unrolling,and array partition is used to design and implement an efficient convolution operation IP core.Finally,the SDx tool is used to integrate the generated IP core into the PL part of ZYNQ.Acceleration of convolutional neural networks.The experimental results show that the ZYNQ-based convolutional neural network hardware acceleration method can effectively implement the hardware acceleration function of the convolutional neural network,and it also shows good performance in the application test based on CIFAR-10 data set.Accelerate performance.