Pulse width modulation for reduced peak power on-chip

Electronic designs are heading towards a system-on-chip (SOC) architecture which incorporates many modules of a system onto a single chip. Sensor network nodes are prime examples of a possible SOC technology where on-chip communication takes up valuable routing and power resources. This thesis explores the design space of a full swing pulse width modulation (PWM) signaling technique for use on-chip to reduce power consumption. Several implementations are discussed and optimized for different goals. A promising implementation was chosen for fabrication in a 0.25mum CMOS process targeting a tiled signal processing array for wireless sensor nodes to demonstrate feasibility. Measurements show a decrease in the worst case power of 7% over traditional binary signaling for 11.8mm long wires at 10Mbps throughput and 0.7V VDD. Power savings are projected to increase to 20% for 30mm long wires, while becoming beneficial for shorter wires at future process nodes without requiring multiple wires or power rails. Power savings occur for wire lengths greater than 1.34mm and reach 20% at 3.03mm at the 32nm node. Savings are also projected to reach 18.2% when used on wires spanning 16 tiles in the target architecture.