A framework for system-level power estimation and optimization of system-on-chip

Minimizing power dissipation is a vital design objective for electrical devices. Various power optimization techniques have been proposed and used to overcome this issue with rapid increases of power. However, it is hard to obtain reliable power saving effects with these techniques at an early design stage, as they are mostly available only at a later stage, at gate level, where a major design change is impossible. In addition, with the shift towards deep sub-micron (DSM) technologies, the increased leakage power and the adoption of power-aware design methodologies have resulted in potentially considerable variations in power consumption under different process, voltage, and temperature (PVT) corners. With all of these causing uncertainty in the predictions of power consumption early in the design stage, it is becoming critical for designers to have credible power estimating frameworks for System-on-Chip (SoC). It is also important for these power models to be usable across various modeling abstractions in an electronic system level (ESL) design flow, in order to guide early design decisions.;In this dissertation, we propose frameworks for power estimation of major components in SoC, and show the feasibility of our methodologies with several case studies. Our unified power modeling methodology for the creation of power models at multiple granularity levels can be quickly mapped to any ESL design flow. The generated models range from very high-level, that can be used in transaction level models (TLM), to extremely detailed, cycle-accurate micro-architectural models. We also propose a methodology that can allow designers to explore the impact of using fine-grained power saving techniques, such as automatic/manual clock gating and operand isolation, at the system level. Furthermore, with our methodology, we can investigate the impact of PVT corners on power consumption at the system level. Given a target technology library, we show how it is possible to scale vertically and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. These models provide a designer significant flexibility to trade off estimation accuracy with estimation/simulation effort. Our methodology allows the exploration of different synthesis "switches," and their impact on power efficiently.