Design and evaluation of an automated test platform for large-scale analog floating gate array programming

Due to advances in microfabrication technology, modern digital systems can process large data sets using discrete algorithms with high precision. However, due to the increasing clock frequencies required to operate on data in real-time applications, analog circuit topologies have become attractive for computation. Such computational blocks require an analog data store that can achieve at least eight hits of accuracy for coarse classification. Thus work creates an automatic means of programming subthreshold floating gate circuits used as analog storage elements. The system consists of a test, platform designed with a flexible configuration for both topology and process-neutral large-scale floating gate array programming. A system-on-chip with analog floating gates has been fabricated in a standard 0.5mum CMOS process and is used to validate the performance of the test platform. A novel algorithm for floating gate programming has been developed based on experimental observation and the test unit is capable of programming analog floating gate arrays to within 0.5% accuracy.