Computer aided design techniques for network-on-chip architectures and system-level low power optimization

System-on-Chip (SoC) integrates several processing cores, ASIC blocks, memory, and communication elements on a single chip. The International Technology Roadmap for Semiconductors (ITRS) predicts that future generations of the high end SoC architectures will be implemented in less than 50nm technology, and clocked in the multi GHz range. These architectures will be composed of tens to hundreds of cores communicating with each other at several Gigabits per second.; Along with performance, power minimization will be an important design goal in nanoscale SoC architectures. Aggressive performance optimization and power minimization techniques will be applied by dividing these architectures into voltage and clock islands. These islands will operate on local clocks. Communication between the voltage islands, also known as global communication, will take place asynchronously, thus obviating the need for a global clock. Such architectures are known as Globally Asynchronous and Locally Synchronous (GALS) based systems.; This thesis addresses two important problems in GALS based SoC design: (i) Design and optimization of global or inter-core communication architecture, and (ii) system-level power minimization. As a primary contribution, the thesis addresses the optimization problems of the communication architecture in the context of a new communication paradigm to meet the performance requirements in future SoCs. As a secondary contribution, it addresses the problem of low power mapping and scheduling in multiprocessor SoC architecture. We propose mathematical models, heuristic techniques, and provably good polynomial time algorithms to solve the optimization problems of future SoC architectures.; Network-on-Chip (NoC) has been proposed as a solution for the global communication challenges in GALS based architectures. NoC supports asynchronous transfer of data, and given a suitable topology, can provide extremely high bandwidth by pipelining signal transmission, and by supporting concurrent communication. This thesis presents techniques for the design of low power NoC architectures, under performance constraints.; Dynamic voltage scaling (DVS), and dynamic power management (DPM) are two well known system-level power minimization schemes that are employed at the board level. GALS based SoC architectures will also support these power minimization techniques. The thesis presents techniques that integrate DVS and DPM with algorithmic transformations namely, pipelining and loop unrolling to minimize the power consumption of a multiprocessor GALS based architecture, under performance constraints.