| This thesis describes how the efficiency of the circuit can be increased in real-time programmable devices. We have designed a re-configurable hardware circuit for the serial-parallel multiplier which uses radix-2 redundant number system as its mode of inputs and outputs. This involves designing a serial-parallel multiplier in which one input is given in parallel in two's complement form while the other is in radix-2 redundant form and is given in serial. The output is obtained in serial as a radix-2 redundant number. The partial products are added by special adders proposed in the thesis. It involves optimizing different FPGA circuits particularly for this architecture and comparing the different results so that the circuit is available for many applications as an IP core. |
