High-Order Phase-Locked Loop Design and Test for Time-Mode Signal Processing Applications

This thesis first presents a pole-zero placement algorithm for the systematic design of high-order phase-locked loops (PLL) serving as anti-imaging and anti-aliasing filters for time-mode signal processing applications. A 6 th order PLL is designed and fabricated on a printed circuit board and is interfaced to a production mixed-signal tester. The correct filtering operation and large-signal transfer characteristic of the PLL are verified with an all-digital DFT solution. The digital test input is driven by a single clock, which can be programmed directly from an ATE high-speed digital pattern generator. As application of these high-order PLLs, an accurate and low-cost clock delay generation system is presented. With proper compensation and calibration, a delay resolution of 15 ps is achieved over an 8.4 ns range. This technique is shown experimentally to be a viable solution for clock alignment and for measuring jitter at a 50 GHz effective sampling rate.