Layout of a low latency hybrid serial-parallel multiplier using TSMC 0.25mum technology

The most attractive features in any Very Large Scale Integration (VLSI) implementation are undeniably small delay times and simplicity of architecture. Various attempts have been made to achieve these characteristics to achieve the most optimum topology for a multiplier. The multiplication operation is one of the most vital operations in many signal processing areas and hence the need for the optimal architecture in terms of VLSI implementation is obvious. Therefore, a new hybrid, low-latency, serial-parallel multiplier was introduced. This multiplier has the combined advantages of reduced clock speed in every cycle, more compact design and lower initial delay times as compared with the previous multipliers. Furthermore, this multiplier has the option of performing operations with Most-Significant-Bit (MSB) first as opposed to Least-Significant-Bit (LSB) first designs.