Modeling and synthesis of the HD photo compression algorithm

The primary goal of this thesis is to implement the HD Photo encoding algorithm using Verilog HDL in hardware. The HD Photo algorithm is relatively new and offers several advantages over other digital still continuous tone image compression algorithms and is currently under review by the JPEG committee to become the next JPEG standard, JPEG XR.;HD Photo was chosen to become the next JPEG standard because it has a computationally light domain change transform, achieves high compression ratios, and offers several other improvements like its ability to supports a wide variety of pixel formats. HD Photo's compression algorithm has similar image path to that of the baseline JPEG but differs in a few key areas. Instead of a discrete cosine transform HD Photo leverages a lapped biorthogonal transform. HD Photo also has adaptive coefficient prediction and scanning stages to help furnish high compression ratios at lower implementation costs.;In this thesis, the HD Photo compression algorithm is implemented in Verilog HDL, and three key stages are further synthesized with Altera's Quartus II design suite with a target device of a Stratix III FPGA. Several images are used for testing for quality and speed comparisons between HD Photo and the current JPEG standard using the HD Photo plug-in for Adobe's Photoshop CS3. The compression ratio when compared to the current baseline JPEG standard is about 2x so the same quality image can be stored in half the space. Performance metrics are derived from the Quartus II synthesis results. These are approximately 108,866/270,400 ALUTs (40%), a 10 ns clock cycle (100 MHz), and a power estimate of 1924.81 mW.