JPEG Implementation Of Still Image Compression Technique

The still image compression has a sound development with the rapid application of multi media technique. Its application mainly focuses on the store and transmission of images, but we find that its frequency band will be widely increased, the bit rate is very high, and the still images occupy more and more space when the analog value is digitized.The most popular algorthem by now is JPEG, which is mainly referred to baseline mode JPEG and JPEG2000 in this thesis.Here we implemente an ASIC chip of JPEG standard. In this paper, we firstly introduce the theory of JPEG compression algorithm. Afterwards, we verify the feasibility of this theory in software. In the last part, we give the detailed implementation of our ASIC chip, including global architecture design, module design, simulation, synthesis, physical layout and formal verification. In the every step, an elaborate analysis is presented.This design of this paper is implemented by Verilog hardware description language and various eda tools.At last,we obtain the netlist and GDSII file of the design.According to the reports, our layout amounts to about 300 thousand standard cells and the chip can run at 100 MHz,the compression ratio is about 9:1 by software verification.