| As integrated circuits are becoming more dense and complex, the simulation speed has become a bottleneck in the verification process. Verification engineers are in need of some simulation techniques that can speed up the process.; In this thesis, I present a framework to optimize the simulation time, by successfully offloading one of the blocks (i.e., sub module of Integrated Circuit Verilog Code) from the main code during simulation. I am proposing a framework for the distributive simulation of Verilog code, using a software agent based approach. The designed framework, called PBELDS (Python Base Environment for Lining Distributed Simulation), allows simulations to communicate data resources flawlessly with each other. This helps the simulation by offloading one of its blocks from the main Verilog code. Synchronous data exchange is maintained all time. This thesis presents a new framework of synchronous distributive simulation technique by implementing PBELDS in Floating Point Unit (FPU) [8] code. |
