A Verilog To C Translate Tool For Godson RTL

Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. In IC design, it is a common method to set up behavior models for target systems by RTL(Register Transfer Level) Verilog codes. People can find the potential logic bugs and primarily evaluate the performance of target systems by deploying software simulation for RTL codes.Currently, many IC design engineers choose commercial simulation software. But the commercial simulation tools are not fit for the general application, such as performance analysis and system evaluation, because of their high costs and complex environment. For general application, developing proprietary simulation tools for special target systems can reduce the costs, simplify simulation environment and accelerate simulation procedure.The research work in this thesis is to design and implement a translator from RTL Verilog codes to C codes, aiming at special lexical and semantic characteristic. We also performance the high level programming language building simulation based on this translator. In the first part of this thesis, we introduce the analysis flow in the front end of the translator. The important data structure and algorithm in each step are discussed. The second part of this thesis is to descript the code generating flow in the back end of the translator. The simplified simulation model and its implementation method are given in this part. Then, we propose the operation optimization method and optimization principles of memory accessing for generating codes. Finally, the generated codes are tested, and the experimental results are provided in this thesis.As a part of the research work of Godson CPU group in Institute of Computing Technology, Chinese Academy of Sciences, the results of this thesis is applied to performance analysis and system evaluation in early design of the Godson CPU.