Dynamic voltage and frequency scaling for energy-efficient system design | | Posted on:2006-06-02 | Degree:Ph.D | Type:Thesis | | University:University of Southern California | Candidate:Choi, Kihwan | Full Text:PDF | | GTID:2452390008462665 | Subject:Engineering | | Abstract/Summary: | PDF Full Text Request | | Demand for low power consumption in battery-powered computer systems has risen sharply. This is due to the fact that extending the service lifetime of these systems by reducing their power dissipation is a key customer requirement. Dynamic voltage and frequency scaling (DVFS) techniques have proven to be a highly effective in achieving low power consumption in various computer systems. The key idea behind DVFS technique is to adaptively scale the supply voltage level of the CPU so as to provide "just-enough" circuit speed to process the system workload while meeting total computation time and/or throughput constraints, and thereby, reduce the energy dissipation.; This thesis presents intra-process DVFS techniques targeted toward both non real-time and real-time applications running on embedded system platforms. To enhance the amount of the CPU energy saving by DVFS, a technique called "workload decomposition" is proposed whereby the workload of a target program is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the CPU clock cycles that are required to execute instructions inside the CPU, whereas the off-chip workload captures the number of external memory access clock cycles that are required to perform external memory transactions. When combined with a DVFS technique to minimize the energy consumption, this workload decomposition method results in higher energy savings for memory-intensive applications. Notice that on-chip and off-chip workload cause different amount of power dissipation because on-chip workload requires the CPU to be executed while off-chip workload requires a proper system component such as memory. So, if the task workload is decomposed into on-chip and off-chip component, the system energy variation according to the CPU frequency can be predicted very accurately, which enables the development of a more effective DVFS approach for the system energy reduction.; The proposed techniques have been implemented on two real computing systems: (1) the XScale-based embedded system platform built at USC and (2) the PXA255-processor based BitsyX system from ADS Inc. Energy savings with the proposed DVFS policies have been obtained by performing current measurements on real hardware. | | Keywords/Search Tags: | System, Energy, DVFS, CPU, Workload, Frequency, Voltage, Power | PDF Full Text Request | Related items |
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