A design methodology for a point of load converter for a distributed power architecture using a normally off silicon carbide vertical junction field effect transistor as the enabiling technology

A point-of-load converter was designed for a distributed power architecture using a normally off silicon carbide (SiC) junction field effect transistor (JFET) as the enabling technology. The power supply accepts a 208-V single phase input and generates a +26 V and +10 V output for pulsed loads as well as a +5 V and -5 V auxiliary supplies for digital/control circuitry. This work focuses on the integration of the first normally off SiC JFET to allow for an efficient (≥ 93%), high power density (≥ 100 W/in3) power converter demonstrating higher switching frequency. A switching frequency of 500 kHz was achieved which more than doubles the operating frequency of a reference design with silicon MOSFETs. The power supply design described in this thesis integrates a power factor correction pre-regulator with multiple output Weinberg and flyback converters each utilizing normally off SiC JFETs. Experimental results are presented to validate the design.