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Performance dependence on the nonlinearity and architecture of the room temperature ballistic deflection transistor for logic applications

Posted on:2012-01-01Degree:Ph.DType:Thesis
University:University of Massachusetts LowellCandidate:Kaushal, Vikas KFull Text:PDF
GTID:2452390008496768Subject:Engineering
Abstract/Summary:
Advancement in the facilities, tools, materials and techniques has guided device technology to grow faster and economical. Exotic materials, innovative ideas and novel devices are few examples of this development. In this thesis, few initial novel ballistic devices and their utilization in logic operations are discussed. In the same context, I present a novel device called ballistic deflection transistor (BDT). The overview, principle of operation and technological processes to fabricate BDTs are discussed.;An exclusive advantage of the technological processes of BDT is that its smallest features can be defined by employing one-step e-beam lithography, which in turn makes it easy to fabricate and analyze. Therefore, BDTs with three different processes are fabricated and analyzed. Standard DC experimental measurements are performed at room temperature and a novel concept for ATLAS 2-dimensional Hydrodynamic Silvaco modeling is used. The nonlinearity in BDT is studied using DC measurements. Since BDT has a top drain which is different than other previously proposed ballistic devices, its importance is also investigated. The effect of geometry modifications and biasing on the device performance in terms of output, leakages and transconductance are studied. The trench filled with high k dielectric is employed to study the gate-channel coupling. A compact fit-based analytical model to aid circuit design using BDTs is also introduced in this thesis. The possible application of such devices in future nanoelectronics is also investigated. Circuit design using BDTs are developed using three different approaches.
Keywords/Search Tags:BDT, Ballistic, Device, Bdts, Using
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