Evaluation of a three-level FeRAM

Ferroelectric random-access memories (FeRAMs) face a big challenge in terms of larger cell area and larger chip area because of the drivers and wiring required for the platelines. This research proposes an idea of multilevel storage (3 levels per cell) in FeRAM, similar to multilevel storage in flash memories. This work addresses some of the major challenges in implementing such multilevel storage. In particular read and write mechanisms for such a multi-level cell are investigated. A parameter sensitivity analysis is done to demonstrate the feasibility of three-level FeRAM operation in the presence of inevitable parameter variations in the cell array. Probability distribution function plots are presented for studying the voltage distribution of the various signal levels. Noise margins of ∼100mV are achieved between the signal levels with readout voltage variations of around 20-30%. Three-level data signaling increases the storage density for 1T1C cells by up to 50%. Issues relating to stable cell operation, along with technological and design constraints are discussed. Finally, some techniques to overcome these issues are proposed like auto-calibrated reference voltage generation scheme and damped oscillating wave bitline voltage driver.