Design and synthesis for low-power FPGAs

With the exponential growth of the performance and capacity of integrated circuits, power consumption has become one of the most constraining factors in the IC design flow. FPGAs (field programmable gate arrays) in general are not power efficient because they use a large amount of transistors to provide post-fabrication programmability in the chip. The goal of our research is to reduce FPGA power consumption and minimize the potential performance loss through architecture design and synthesis across various optimization levels. Our research spectrum covers two major directions:; Design and synthesis for power optimization for existing FPGAs . (1) FPGA power modeling and architecture evaluation; (2) Logic synthesis for FPGA power minimization; (3) High-level synthesis for FPGA power minimization; (a) LOPASS---an architectural synthesis system; (b) xPlore-Power---a resource allocation and binding algorithm.; Design and synthesis for novel power-efficient FPGAs. (1) Logic synthesis for power-efficient FPGAs; (2) High-level synthesis for power-efficient FPGAs.; In our nomenclature, existing FPGAs are FPGA architectures that contain no specific architectural features for power efficiency. For these types of architectures, we have three research thrusts. Power modeling sets up a power-evaluation flow using gate-level power estimation. Logic synthesis concentrates on FPGA technology mapping and circuit clustering. High-level synthesis includes two projects. LOPASS is the first full-blown academic high-level synthesis system specifically designed for FPGA power minimization. xPlore-Power concentrates on resource allocation and binding targeting a commercial FPGA architecture. The second major direction studies how FPGA architecture itself can offer further power reduction. We design novel power-efficient FPGAs, which support multiple supply voltages and power-gating features. We have two thrusts under this category. We first incorporate dual-Vdd scenarios into our mapping and clustering algorithms. Our work represents the first effort in the study of delay-optimal low-power mapping and clustering considering dual supply voltages. We then apply multiple supply voltages for high-level synthesis. We derive a polynomial-time optimal algorithm for simultaneous functional unit binding and voltage assignment. At the end, we draw some important conclusions on power reduction potentials of different synthesis stages for different FPGA architectures.