Test infrastructure design for digital, mixed-signal, and hierarchical SOCs

Manufacturing test is a major contributor to system-on-chip (SOC) production cost. The increasing reliance of SOC designers on third-party and company-internal intellectual property (IP) blocks, also referred to as embedded cores, has greatly exacerbated the test problem. The rising test cost for SOCs can be attributed to ever-increasing complexity, limited test access to the embedded cores from chip pins, high test data volume, and the lack of knowledge of the internal details of IP cores. As a result, there is a pressing need for methodologies and tools that can provide effective solutions to the SOC test problem.; Current-generation SOCs contain a heterogeneous mix of embedded cores, which include not only flat (non-hierarchical) digital modules, but also analog and hierarchical modules. The increase in SOC complexity has also been accompanied by the development of more versatile automatic test equipment (ATE). This thesis presents methods for modular test of heterogeneous SOCs, whereby test cost is reduced by combining effective test infrastructure design with efficient utilization of ATE resources. Test infrastructure design refers to the design and optimization of test wrappers and test access mechanisms, as well as test scheduling for efficient resource utilization.; The thesis first presents test infrastructure design methods that exploit the availability of port-scalability in current-generation ATEs. Port-scalable ATEs allow the simultaneous transfer of test data at multiple scan data rates. A virtual TAM design is presented that matches the ATE channels operating at high data rates with the low-speed scan frequencies of the embedded cores. A test planning method for a dual-speed TAM architecture is also presented. In addition, test planning methods that exploit the availability of two or more data rates for ATE channels are explored for SOCs that contain embedded cores in multiple clock domains.; This thesis next presents test infrastructure design methods for high-volume mixed-signal SOCs that operate at low frequencies. A novel analog test wrapper design is used to convert analog cores into virtual digital cores, this design reduces the need for expensive mixed-signal testers and allows the test of both digital and analog cores in a unified manner. The analog test wrappers use front-end and backend data converters to translate digital test patterns into analog test stimuli, and analog responses into digital responses, respectively. A redesign methodology is also presented that reduces the design effort required for analog data converters. The redesign method reduces design time for the test infrastructure, thereby helping to reduce test cost.; Finally, new test infrastructure designs are presented for hierarchical SOCs. First, a fully-testable, area-efficient, and IEEE P1500-compliant wrapper for hierarchical cores is presented. The new wrapper design is then incorporated in a SOC-level TAM optimization and test scheduling method. The TAM optimization problem is formulated for two practical design scenarios, which relate to the ease with which the embedded child cores in parent cores can be modified by the system integrator.; The framework presented in this thesis reduces the test cost for SOCs that fall in the high-volume, low-profit margin, and increasingly competitive commodity market. The proposed test infrastructure design methods will allow system integrators to exploit the benefits of high performance, low power consumption, greater product functionality, and shorter design cycles, which are offered by the core-based SOC design paradigm.