| The crystallization of hydrogenated amorphous silicon (a-Si:H) deposited by plasma enhanced chemical vapor deposition (PECVD) by thermal annealing is of great interest for display and silicon-on-insulator (SOI) technologies. For large area electronics, there has been considerable interest to integrate both a-Si:H TFTs, for low leakage in the OFF state, and poly-Si TFTs, for high drive currents, on the same substrate, for example, to integrate polysilicon drivers in flat panel displays using a-Si:H TFTs in pixels. There is interest also to achieve high mobility polysilicon TFTs fabricated at low temperatures (≤600°C). Low thermal budgets are necessary so that glass substrates can be used in case of display applications, and damage to preexisting devices is minimized in case of 3-D integrated circuit applications. In this thesis we will describe the use of selective crystallization using hydrogen plasma seeding treatment of a-Si:H layers to achieve both these aims.;We have found that a room temperature hydrogen plasma exposure in a parallel-plate-diode type Reactive Ion Etcher (RIE) can reduce crystallization time of a-Si:H by a factor of five. Exposure to hydrogen plasma reduces the incubation time, while the rate of crystallization itself is not greatly affected. This plasma enhanced crystallization can be spatially controlled by masking with patterned oxide, so that both amorphous and polycrystalline areas can be realized simultaneously at desired locations on a single substrate. The enhancement of crystallization rate is probably due to the creation of seed nuclei at the surface and the effect is limited to the top 30--40 nm of the a-Si:H layer.;We have used these films to fabricate low temperature (600°C) self-aligned n-channel polycrystalline transistors. Well-behaved characteristics were obtained in all cases. All the samples had mobilities in the range of 35--40 cm 2/Vs despite the short crystallization time in the hydrogen-plasma treated sample.;Lateral seeded growth from seeded regions in the source and drain regions resulted in higher performance TFTs with the field-effect mobility increasing for channel lengths shorter than 5 mum. The seeding was done by exposure to hydrogen plasma after the active region and the gate was patterned. The seeded-low-temperature TFTs had a field-effect mobility of ∼75 cm 2/Vs for channel length of ∼2 mum, nearly twice that of unseeded TFTs.;We have demonstrated a method for integrating a-Si and poly-Si transistors together starting with a single Si layer with no laser processing involved, combining many of the fabrication steps between the two transistors, so that making both a-Si:H and poly-Si TFTs of high performance is not much more work than making just one type of transistor. |
