Parameter extraction for electronic packaging and decoupling methodology for power delivery systems

In modern integrated circuits and packaging analysis, it is often significant to determine frequency-dependent resistance and inductance per-unit-length parameters of transmission lines. With ever increasing integrated-circuit speeds, it is desirable to have efficient algorithms for accurate computation of frequency-dependent parameters in both low and high frequencies. In this dissertation, a quasi-static approach based on PEEC (Partial Element Equivalent Circuit) method for frequency-dependent resistance and inductance calculation of interconnects is presented. The numerical meshes proposed automatically conform to the electric current distribution inside the conductors as frequency varies. It is found that, even for very high frequencies, only a small number of mesh elements inside a conductor is required to generate accurate computational results, and therefore considerable savings in computer resources can be achieved. The comparison of the results of our method and FastHenry is presented. Finally, a detailed derivation for two-dimensional partial inductance is demonstrated since 3D formulation can easily suffer from numerical instability for very long conductors.; On the other hand, as clock and data frequencies increase while the rise and fall time decrease, to build a noise-free or low noise power delivery network becomes an increasingly difficult challenge for modern PCB and IC designs. Without stable and adequate power, high-speed devices behave unpredictably. The impedance of power distribution system (PDS) can be controlled over a wide range of frequencies through the careful consideration of design of the switching power supplies, decoupling capacitors, and power and ground planes. However, this work has long time been dependent mainly on rules-of-thumb and the designer's experience. In the second part of the thesis, a systematic and automatic scheme for decoupling capacitor placement on printed circuit boards has been developed. The proposed scheme can intelligently choose the correct capacitors and best locations to achieve a low impedance profile for the PDS. An actual complex design example is given to demonstrate the effectiveness and robustness of the presented methodology. The optimized decoupling capacitor placement not only provides much lower power ground impedance, but the time-domain noise is also significantly reduced.